1. Field
An embodiment of the present invention relates to the field of data transmission and, more particularly, to transmitting data in high frequency integrated circuits.
2. Discussion of Related Art
Computer systems continue to include additional capabilities while being capable of operating at higher and higher frequencies. As operating frequencies increase, integrated circuit design becomes increasingly difficult.
As a specific example, a prior video controller integrated circuit 100 is shown in FIG. 1. The video controller 100 includes a video control core 105 that generates video data signals in response to instructions executed by a microprocessor (not shown). Video output data is to be provided to an external receiver 110 by a transmitter 115. For a typical design, the video control core is located near the center of the host integrated circuit while the transmitter is located near the periphery of the chip.
For very high operating frequencies, the signal path between the video control core 105 and the transmitter 115 can be problematic. The transmitter 115 receives both true and complementary forms of the input data from the video control core. True data (DATA IN) is provided to the transmitter 115 over the signal path including data buffers 120 and 121 while complementary data is provided to the transmitter 115 over the signal path including data buffers 123, 124 and 125. Because the signal paths for the true and complementary data paths are asymmetrical (i.e. the delay for the complementary path is longer than the delay for the true path), true and complementary data arrive at the transmitter 115 at different times, potentially incurring a “noise glitch” or asymmetrical delay to provide a valid output signal. The effect of asymmetrical delay through the transmitter or asymmetrical switching of the transmitter is similar to noise injected into the transmitter. The delay between the true and complementary paths can be equalized for a particular process corner by carefully sizing the data buffers 120, 121, 123, 124 and 125, but the delays through the paths will then vary for different processes and/or different operating parameters.
The video controller 100 also includes design for testability (DFT) logic to facilitate testing of the video controller. For the video controller 100, an internal DFT receiver 130 receives the output signal(s) from the transmitter 115 and provides an amplified output signal to combinatorial logic 135. The combinatorial logic 135 converts the amplified output signal to a digital signal that is latched by a flip-flop 140 or other latch in the video control core 105. The latched signal is then compared to an expected value to determine whether the transmitter 115 and/or other logic is operating properly.
Again, at very high operating frequencies, the DFT signal path of the video controller 100 may present issues in latching the correct data. For example, at an operating frequency of 800 MHz, data needs to be sent from the core logic 105, through the transmitter 115 and the internal DFT receiver and back to the flip-flop 140 in the video control core 105 all within one clock cycle or 1.2 ns. With long signal paths and associated noise, meeting this timing requirement may not be straightforward.